1. Field of the Invention
This invention generally relates to digital envelope-framed communications and, more particularly, to a system and method for filtering buffer-fill information that is used in the calculation of stuff bit opportunities for loading data tributaries into a Synchronous Payload Envelope (SPE).
2. Description of the Related Art
In a synchronous communications network, digital payload data is carried at a particular clock frequency within a synchronous message format. This payload data may include both asynchronous digital data and synchronous digital data originating at a different data rate in a foreign digital network. The Synchronous Optical Network (SONET), and its European counterpart the Synchronous Digital Hierarchy (SDH), provide a standard format of transporting digital signals having various data rates, such as a DS-0, DS-1, DS-1C, DS-2, or a DS-3 signal and their European counterparts within a Synchronous Payload Envelope (SPE), or a container that is a part of a SONET/SDH STS-N/STM-N message frame. In addition to the digital data that is mapped and framed within the SPE or container, the STS-N/STM-N message frame also includes overhead data that provides for coordination between various network elements, and permits data delineation.
One of the benefits of SONET is that it can carry large (high-speed) payloads (above 50 Mb/s). However, the existing slower speed digital hierarchy can be accommodated as well, thus protecting investments in current equipment. To achieve this capacity, the STS Synchronous Payload Envelope (SPE) can be sub-divided into smaller components or structures, known as Virtual Tributaries (VT) for the purpose of transporting and switching payloads smaller than the STS-1 rate. All services below the DS3 and E-3 rates are transported in the VT structure.
In SONET there are four sizes of virtual tributaries, a VT-6 (12 columns of data), VT-3 (6 columns of data), VT-2 (4 columns of data), and VT-1.5 (3 columns of data). A virtual tributary group (VTG) is formed of a single type of VT and by definition each VTG contains 12 columns of data. Thus, there can be one (1) VT-6, two (2) VT-3, three (3) VT-2, or 4 VT-1.5 VTs per VTG. Because there are 12 data columns per VTG, there are seven VTGs within a single STS-1 SPE, with a column of data providing the path overhead data and two (2) columns of stuff data. The VGs are grouped within a Virtual Superframe that comprises four (4) consecutive STS-1 message frames. The VTGs within the superframe each have varying numbers of VTs within them, and together define a virtual SPE. The VTs contained within the virtual SPE may be operated in a fixed or floating mode. In a fixed mode, the VT SPE mapping into the four (4) STS-1 SPEs comprising the superframe is fixed. This reduces the interface complexity and is designed for maximum efficiency of the network elements. A floating VT mode allows the VT SPE to float within the virtual SPE defined for the VTs. A floating VT requires a VT payload pointer and VT path overhead. In the case of a VT floating within a virtual superframe, the VT payload pointer is defined by bytes, V1 and V2. In addition, payload resynchronization and payload adjustment is accomplished using the V1, V2, and V3 in the same manner as the H1, H2, and H3 bytes in the transport overhead of the STS-1 message as described below.
Similarly, in a SDH STM-1 format, which is based on a 2.048 Mbit/s hierarchy, there is a bandwidth flexible virtual container (VC) that permits the transmission of high-speed packet switched services, ATM, contribution video, and distribution video. In addition, the VC permits transport and networking at the 2 Mbit/s, 34 Mbit/s, and 140 Mbit/s in addition to the 1.5 Mbit/s hierarchy.
The lowest level of multiplexing in a SDH message includes a single container (C). The containers are used to create a uniform virtual container (VC) payload through bit-stuffing to bring all the inputs to the container to a common bit-rate that is suitable for multiplexing in the VCs. There are two levels of VCs. A low level VC, i.e., VC-11, VC-12, and VC-2, includes data at a rate from 1.5 Mbit/s to 6 Mbits/s. Upper level VCs, i.e., VC-3 and VC-4, include data at a rate of 34/45 Mbit/s and 140 Mbit/s. The various VCs are converted into Transmission Units (TUs) with the addition of tributary pointer information. Thus, a VC-11 becomes a TU-11, a VC-12 becomes a TU-12, a VC-2 becomes a TU-2, and a VC-3 becomes a TU-3.
A single TU-2 or 3 TU-12s, or 4 TU-11s are combined into a Transmission Unit Group 2 (TUG-2). Seven TUG-2s can be used to form a VC-3 or a TUG-3. Three TUG-3s are combined to form a VC-4. A single VC-3 or a single VC-4 are converted into an administrative unit three (AU-3) or an AU-4 respectively, with the addition of an administrative unit pointer. Three AU-3s or a single AU-4 are formed into an Administrative Unit Group (AUG). One AU-4, four AU-4s, or 16 AU-4s are formed into an STM-1, STM-4, or an STM-16, respectively. The administrative unit group forms the SPE of the SDH STM-1.
In a floating TU mode, four consecutive 125 microsecond frames of the VC-4 are combined into a single 500 microsecond called a TU multi-frame. The tributary units comprising the TU multi-frame signal also contain payload pointers to allow for flexible and dynamic alignment of the VCs within the TU multi-frame. In this instance, the payload pointer value indicates the offset from the TU to the first byte of the lower order VC. This mechanism allows the AU and TU VC payloads to vary with respect to phase to one another and to the network, while allowing the VCs comprising the AUs and TUs to be synchronously multiplexed. The TU multi-frame overhead consists of four bytes: V1, V2, V3, and V4. Each of the four bytes is located in the first bytes of the respective TU frame in the TU multi-frame signal. The V1 and V2 bytes designate the position of the first byte of the VC, the V3 byte provides a payload pointer adjustment opportunity, and the V4 byte is reserved. Thus each of the VCs within an STM can float relative to one another
If the digital data that is mapped and framed in the STS-N/STM-N is originally carried by a clock signal having a different frequency than the SONET/SDH line rate clock, certain adjustments to the framed digital data must be made. For example, if a DS-3 data signal, which is timed by a 44.736 MHz DS-3 clock signal, is to be carried in a SONET/SDH fiber-optic network, the DS3 signal is mapped into the higher rate SPE of an STS-1, and extra bits must be added to the DS-3 signal prior to transmission through the SONET/SDH network. These extra bits are commonly referred to as stuff bits or gap bits, and are place markers and may, or may not carry valid data. These gap bits are required because the DS-3 signal is slower than the SONET/SDH clock frequency, so that there are not enough DS-3 bits at the higher frequency to form a complete SONET frame. More detail may be found in the Bellcore specification “SONET Transport Systems: Common Generic Criteria”, GR-253-CORE, Issue 3, Sep. 2000, the Bellcore specification “Transport Systems Generic Requirements (TSGR): Common Requirements”, GR-499-CORE, Issue 2, Dec. 1998, and the ITU-T Recommendation G.783, “Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks”, January 1994.
When the STS-1 is received at a network exit node, the overhead bytes are removed from the SONET STS-1 and replaced by gaps in the data stream. The payload data that remains is de-framed and de-mapped into a data stream carried at a higher clock frequency than the nominal original clock frequency of the payload data. The stuff data that was inserted when the data was mapped into the SPE remains when the data stream is recovered from the SPE, and is also replaced by gaps in the data stream. Thus, the recovered payload data contains gaps in the data stream remaining after the overhead bytes and stuff data bits have been removed. If, for example, DS-3 data has been transported via a SONET/SDH network, the DS-3 data must be converted from the SONET clock signal to the lower frequency DS-3 clock signal and the gap data bits must be removed prior to the DS-3 signal being B3ZS-encoded for electrical re-transmission.
To transfer data from one clock domain to another, for example from the DS-3 embedded within the SONET signal rate to the proper DS-3 signal rate, a desynchronizer is used to provide a buffering mechanism between the clock domains. A desynchronizer typically includes an elastic store first-in-first-out memory buffer that receives gapped data recovered from a synchronized data payload as an input at one clock frequency and stores the data in appropriate storage locations. The desynchronizer also includes an output mechanism that reads data out of the buffer at a uniform data rate, without the gaps.
Although the SONET/SDH fiber optic network is a synchronous network, variations in clock signals across the network may occur. These variations in clock signals between various network elements may cause a loss of data downstream from the sender if the clock signal at which data is written to the synchronous payload and the clock signal at which the data is read from the synchronous payload are sufficiently different. A variety of conditions can cause variations in clock signals. For example, network clock instability, electrical noise and interference, effective changes in the length of transmission media, changes in the velocity of propagation, Doppler shifts, irregular timing information, and other electrical and network problems may all cause clock variations.
To mitigate the problems caused by clock variations across a network, the SONET/SDH STS-N/STM-N messages are provided with a pointer adjustment mechanism within the transmission overhead bytes that permit some movement of the data within the SPE. The pointer adjustment mechanism includes a pair of bytes, H1 and H2, which identify the start of the next SONET/SDH payload byte and also indicate if the pointer adjustment byte, H3, is to be used. The third overhead byte (H3) provides for active pointer adjustment when a negative justification of the SPE is required. Negative justification involves posting valid data in the H3 byte. Positive justification involves marking the byte after the H3 byte as a dummy or stuff byte. These pointer adjustments allow for eight (8) bits of data to be added to a SONET/SDH message frame (using the H3 overhead byte) or for eight (8) bits to be removed from the frame. This allows for the SPE to be re-framed and re-synched at a network node that has a slightly different network clock. Thus, in addition to the gap data necessary to compensate for payload data that is carried by a different frequency clock signal, eight bits of data may be added or removed at each network element in the network due to clock instability in the network.
Pointer adjustments can be periodic or aperiodic in nature. A periodic pointer adjustment may be caused, for example, when, the SPE transporting the data has a constant clock offset at the output node of the network relative to the input node. An aperiodic or non-periodic pointer adjustment may be bursty in nature when caused by a transient problem or condition within the network.
Although the synchronous system may adjust the payload data using pointer adjustments to account for clock and phase variations, the clock and phase shifts caused by the pointer adjustments and/or the de-gapping of the payload data can affect the output rate of the data clock provided by the PLL. Typically, clock and phase shifts have two components. One is a high frequency jitter component that is classified as a clock or phase shift that is greater than, or equal to 10 Hz. A second is a low frequency wander component that is classified as a clock or phase shift that is less than 10 Hz.
Jitter refers to the phase variations in the clock signal, which may cause errors in identifying bit positions and values accurately, and is therefore an issue in synchronous systems. The jitter requirement for SONET can be found in the ANSI document “Synchronous Optical Network (SONET)—Jitter at Network Interfaces”, ANSI-T1.105.03-1994. Wander refers to phase variations that typically affect the frame and time-slot synchronization. The wander requirement for SONET can be found in the ANSI document “Synchronous Optical Network (SONET)—Jitter at Network Interfaces—DS3 Wander Supplement”, ANSI-T1.105.03b-1997. Each network element adds some amount of noise to the SPE that eventually contributes to the timing instability in the form of jitter and wander in the recovered payload signal.
As is known, the PLL used to recover the smooth clock signal and smooth data signal is able to smooth out some phase jumps caused by pointer adjustments or asynchronous stuff bits. A PLL is most effective at filtering out high frequency jitter components, i.e., those with a frequency greater than 10 Hz, but is less effective at filtering out the low frequency wander components. Since, typically the wander components are much less than 10 Hz, these wander components are well within the bandwidth of the PLL and are passed without being attenuated. To construct a PLL with a small enough bandwidth to filter the wander components of the phase jumps, large time constants in the PLL control loops would require large component values for the resistors and capacitors used in the PLL. In addition, the large time constants required would result in a PLL that is slow to lock onto the reference signal and would cause long delays in recovering lock after a transient event.
One source of wander errors in the output data rate can be caused by the pointer adjustments within the synchronous signals. Each pointer adjustment signal or asynchronous gap data results in a data gap for a given number of clock cycles. For example, an 8-bit pointer adjustment that occurs once a second or less, is a low frequency change in the data rate.
When a pointer adjustment is received however, there are eight bits that are added to the elastic store, or skipped, and not written to the elastic store. The inconsistent nature of the gapped data can result in large changes in the data output rate. The ratio between the input data rate and the output data rate may change by a value sufficiently large that the elastic store can experience a data overflow condition or a data underflow condition. Data overflow occurs when data is written to the elastic store at a faster rate than usual, or read at a slower rate than usual, causing the elastic store to accumulate data. In these conditions, the elastic store may be unable to store all of the incoming data, and data may be lost. Similarly, data underflow occurs when data is written to the elastic store at a slower rate than usual, or read at a faster rate than usual, causing the elastic store to lose data. In this circumstance no data is read from the elastic store.
Typically, the elastic store used in the desynchronizer is a FIFO buffer with a write/read control system that attempts to maintain the output data rate at a specified rate, and maintain the elastic store at a predetermined fill level. If the elastic store begins to overfill, the write/read control system increases the data output rate of the elastic store until the proper storage level in the elastic store is reached. Once the proper storage level is reached, the write/read control system decreases the data output rate. If the elastic store begins to underfill, the write/read control system will decrease the data output rate of the elastic store until the proper storage level in the elastic store is reached. Once the proper level is reached, the write/read control system increases the data output rate.
As noted above, the VT or TU-11/12 pointer bytes V1, V2, and V3 operate in the same manner as the H1, H2, and H3 pointer bytes described herein. Similar problems related to the processing of the VT pointer bytes occur, and the positive justification of the VT pointer bytes is accomplished by assigning the bytes immediately after the V3 bytes as positive stuff opportunity bytes. Negative justification is accomplished by assigning the V3 byte to contain valid data. The frequency and polarity of the pointer adjustments to the VT pointer bytes is uncorrelated to the frequency of the pointer adjustments made by the SONET/SDH H1-H2-H3 pointer bytes. In addition, the wander and jitter associated with the pointer adjustments is also uncorrelated between the transport overhead pointer bytes and the VT overhead pointer bytes.
The highly non-uniform input data rate to a SONET SPE is primarily due to the presence of transport overhead (TOH) and the position of data bits and stuff bits in the SONET SPE. The TOH data is not provided as output data since the de-mapper in the SONET receiver only provides a write enable signal when valid data from the SPE is present. Thus, there may be long gaps with no data when TOH data is present. As discussed above, stuff bits may be added to the SPE when mapping PDH data into the SONET SPE, to account for different data rates between the PDH data and the SONET data rate. Typically, stuff bits when mapped into the SPE are not valid data and are mapped into known locations. The de-mapper skips over the stuff bits, and a short gap of no data occurs.
A filter and the read enable generator may be used to substantially smooth the non-uniform data input rate. The filter and read enable generator can vary the nominal rate at which read enable signals are generated by controlling stuff opportunities during the data output in which data bits can be added to the nominal data rate, thereby increasing the data rate, or removed from the nominal rate, thereby decreasing the data rate.
The filter and rate enable generator provide an output control word that is indicative of the storage level of tributaries, in preparation for mapping into an SPE. The control word can be the average of the storage level over a predetermined time period, or a value derived from the average or other suitable statistics based on the storage level. For example, the filter may be a low pass filter that averages out fluctuations in the storage level by filtering the high-frequency components to provide the average value, which may be scaled by multiplying it by a predetermined constant, as the control word.
A mapper may be used to map data channels into frames defined by network protocol, where adjacent frames are separated by a frame boundary. For example, PDH tributaries may be mapped into SPEs using SONET protocol.
FIG. 1 shows a closed loop system used for phase attenuation or data-rate recovery (prior art). Incoming data is written into a buffer. The buffer-fill is filtered to generate a control signal that drives a rate generator. The rate generator produces a read signal, which is used to read data out from the buffer. The operation of this system is such that the output rate is made to match the incoming rate, which effectively recovers the data rate. The closed-loop transfer function of the system can also be arranged such that the output data rate, though on average the same as the input data rate, is much smoother than the incoming data rate, which is typically noisy due to data transmission effects such as mapping and demapping.
FIG. 2 shows a variation of the system shown in FIG. 1, in which the buffer fill signal is modulated (prior art). This “threshold modulation” concept is typically used for making bit-stuff decisions in systems without filters, by comparing the buffer-fill against a varying threshold, which is equivalent to modulating the buffer-fill and comparing that result against a threshold. Then, a stuffing (or not stuffing) decision is made depending on the result of the comparison. This method is not preferred because it can produce high levels of output wander. The system is not especially effective when filters are used, and does not remove the effect of limit cycles (discussed below). Also, each channel (buffer) requires an independent filtered buffer-fill signal, which results in a large amount of hardware if the system is multi-channel.
FIG. 3 shows a variation of the system shown in FIG. 1, in which the output read-enable signals are modulated (prior art). For example, a “dither” signal can be applied to the read-enable as a variation of the threshold modulation scheme. As in the system of FIG. 2, a multi-channel system requires a separate modulation circuit for each buffer, which results in duplicated hardware circuits. Further, it is not apparent that such a design may be used in systems that directly calculate the stuff control signals that are sent to the mapper (instead of the entire read enable signal being sent to the buffer).
The systems shown in FIGS. 2 and 3 may be analog or digital. In a fully analog system, the filter can be an analog filter, and the rate generator can be a voltage-controlled-oscillator (VCO). As described in parent application Ser. No. 10/346,550, in a digital system the filter can be a digital filter, and the rate generator can be a digitally-controlled oscillator. A combination of analog and digital components may also be used (analog filter+analog-to-digital converter+digital rate generator, or digital filter+digital-to-analog converter+VCO).
The use of a digital loop filter in a desynchronizer or jitter-attenuator can result in high jitter spikes due to limit cycle behavior. This limit cycling phenomenon is a well known problem associated with closed-loop systems that use digital control signals. The normal solution to the limit cycling problem is to change the form of the filter, but this solution requires more hardware, which is a disadvantage in high-density applications.
It would be advantageous if a hardware-efficient method existed for controlling the impact of limit cycles, and reducing output jitter in jitter attenuation systems.